• Lab Assistant for:

           - 2017, Electronics Basics

           - 2017, 2018 Atomic and Molecular Physics

           - 2016, Quantum Experimental Physics

           - 2015,2016, 2018 FPGA-based digital system construction

           - 2014,2015,2016, 2017, 2018 Radiation detectors and measurement methods

Publications:

• 2023 - Radiation studies performed on the High Luminosity ATLAS TileCal link Daughterboard. Journal of Instrumentation, Volume 18, DOI 10.1088/1748-0221/18/04/C04011

• 2021 - A revised version of the ATLAS Tile Calorimeter link Daughterboard for the HL-LHC. IEEE Transactions on Nuclear Science. DOI: 10.1109/TNS.2021.3103408

  Available: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9508978

• 2019 - Development of the read-out link and control board for the ATLAS Tile Calorimeter Upgrade. PhD Dissertation, Stockholms universitet, Naturvetenskapliga fakulteten, Fysikum. ISBN: 978-91-7797-895-4.

  Available: http://www.diva-portal.org/smash/get/diva2:1364842/FULLTEXT03.pdf

• 2019 - ATLAS Tile Calorimeter Link Daughter Board. Proceedings of Science - TWEPP 2018 - Topical Workshop on Electronics for Particle Physics. DOI: 10.22323/1.343.0024.

  Available: https://pos.sissa.it/343/024/pdf

• 2019 - An updated design of the read out link and control board for the Phase-2 upgrade of the ATLAS Tile Calorimeter. Proceedings of Science - ICHEP - XXXIX INTERNATIONAL CONFERENCE ON HIGH ENERGY PHYSICS Physics. DOI: 10.22323/1.340.0750.

  Available: https://pos.sissa.it/340/750/pdf

• 2019 - Beam Tests on the ATLAS Tile Calorimeter Demonstrator Module. PM2018 - 14th Pisa Meeting on Advanced Detectors. DOI: 10.1016/j.nima.2018.10.066

  Available: https://cds.cern.ch/record/2624587/files/ATL-TILECAL-PROC-2018-001.pdf

  Available: https://www.sciencedirect.com/science/article/pii/S0168900218313809?via%3Dihub

• 2018 - An Updated Front-End Data Link Design for the Phase-2 Upgrade of the ATLAS Tile Calorimeter, 2017 IEEE Nuclear Science Symposium and Medical Imaging Conference. DOI: 10.1109/NSSMIC.2017.8533116.

  Available: https://cds.cern.ch/record/2292072/files/ATL-TILECAL-PROC-2017-021.pdf

  Available: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8533116

• 2017 - Upgrade of Tile Calorimeter of the ATLAS Detector for the High Luminosity LHC. Journal of Physics: Conference Series, Volume 928. DOI: 10.1088/1742-6596/928/1/012024.

  Available: https://iopscience.iop.org/article/10.1088/1742-6596/928/1/012024/pdf

• 2017 - Technical Design Report for the Phase-II Upgrade of the ATLAS Tile Calorimeter ATLAS Collaboration (CDS Preprint). CERN-LHCC-2017-019, ATLAS-TDR-028.

  Available: https://cds.cern.ch/record/2285583

• 2016 - A radiation tolerant Data link board for the ATLAS TileCal upgrade. Journal of Instrumentation. DOI: 10.1088/1748-0221/11/01/c01074.

  Available: https://iopscience.iop.org/article/10.1088/1748-0221/11/01/C01074/pdf

• 2015 - Improvement of the first Cuban laser densitometer. Revista Cubana de Fisica.

  Available: http://www.revistacubanadefisica.org/RCFextradata/OldFiles/2015/Vol32_No2/RCF_32-2_106.pdf

• 2011 - USB and RS232 voltage datalogger. Revista Científica de Ingeniería Electrónica, Automática y Comunicaciones.

  Available: https://rielac.cujae.edu.cu/index.php/rieac/article/view/13/pdf_53

• Experience:

• FPGA Firmware for TileCal Demonstrator: FPGA Firmware was developed for the ATLAS Hadronic Tile Calorimeter (TileCal) Phase-II upgrade TDAQ system. The Xilinx ISE Design suite and Vivado environments were used to develop firmware for the TileCal Demonstrator Read Out Link and Control Board (Daughterboard) and Tile Preprocessor (TilePPr). The Daughterboard interfaces the inner detector electronics with the TilePPr situated off-detector. The firmware includes communication between both boards using GBT protocol via redundant multi-Gbps Optic links powered by GTX, GTH and GTY Gigabit transceivers. Both firmwares allow read out of the TileCal PMT data, control of the on-detector electronics interfaced with the Daughterboard and remote reconfiguration of the Daughterboards and on-detector FPGAs and their respective configuration memories (PROMs). The development included digital design on different Xilinx evaluation boards (VC707, KC705, and KU115) before moving on to prototypes of the developed hardware.

• Testing and Debugging Demonstrator Read-Out Link and Control Board (Daughterboard): Different parts and components of the electronics design for the Daughterboard revisions 3, 4, 5 and 6 were tested. Among others, the tests performed included voltage noise levels of the developed board and interfaced cards, flash/EEPROM radiation tolerance, stability of the communication via the optic links, pedestal stability, charge injection and additional electronic noise. Texas instruments CDCE and CERN GBTx chips clock qualities, in addition to different CERN GBTx chip configurations were studied. The Daughterboard functionalities were also tested with all the upgrade system in testbeam sessions at the SPS at CERN. A testbench for debugging and qualify the Phase-II Daughterboards during development and production phase was put into place with the relevant off- and on-detector electronics. Additionally, a suite of python scripts for running the different tests by communicating the Tile-PPr thought IPBUS and a custom solution based on a Raspberry Pi to test/program/control/fuse the GBTx chips utilized on the Daughterboard were developed.

• Radiation tests for Daughterboard: The revisions 5 and 6 of TileCal Daughterboards were tested for Total Ionizing Dose (TID), Non-Ionizing Energy losses (NIEL), Single Event Latch-ups (SELs) and Single Event Upsets (SEUs) to qualify the electronics components used for the HL-LHC radiation environment. The TID and NIEL included the components of the board and different models of SFP+. The SEU tests characterized the Single Event Errors (SEEs) and the Single Event Latch-Ups (SELs) on the Microsemi ProASIC, Kintex Ultrascale and Kintex Ultrascale+ FPGAs used on the boards and evaluated the recovery strategies in case of non-recoverable errors.

• Upgrade, service and maintenance of the TileCal Legacy Digitizer boards: Tasks for Upgrade of Stockholm testbench for TileCal Digitizer Boards have involved migrating the testbench to a modern FPGA technology. As part of Stockholm University contribution to TileCal, different tests are done to the Digitizer Boards in order to certify them for detector operations. Tasks include the testbench tests and debugging the bad parts of the board in order to be able to repair when possible.

• Diploma Thesis: Energy Loss Behavior due to gluonic radiation in Gamma – Jet events in proton-proton collisions at 14 TeV in ALICE Detectors. Using Root – Aliroot software framework the energy loss due to gluonic radiation in Gamma – Jet events was obtained and analyzed by simulating p-p@14TeV events in PYTHIA. Jets were reconstructed with a properly calibrated cone reconstruction method that estimated background energy with ideal calorimeter and tracking, using PHOS and TPC ALICE detectors respectively. Energy vs transversal momentum, multiplicity and transversal pedestal energy of Jets were obtained. Diploma Dissertation. Faculty of Nuclear Physics, Higher Institute of Technologies and Applied Sciences (InSTEC), July, 2008. Supervisor: Arian Abrahantes Quintana.

• Software for Scientific Instrumentation: Multiple software were developed for scientific instrumentation in multiple programming languages such as LabView, C# and Visual Basic mainly for data acquisition systems such as data logger device which included the control of all the features of the device by USB interface as well as the acquisition of the data saved in the device. Additionally, it was developed the data acquisition software for the Laser Densitometer LD-01, which included the whole control of the device, the data acquisition, analysis and graph of the electrophoresis patterns for protein concentration in blood samples and the report of the results.

• Microelectronics for Scientific Instrumentation: Firmware development for took place using ANSI C Compilers and FPGA programming mainly for data acquisition systems. It was developed a firmware for Voltage Data logger DL-01, which controls the all the actions of the device as well as communication by USB or RS232 interface with a PC. Additionally, it was developed a firmware for a Laser Densitometer Device, which controlled the movement of a motor moving a laser while sampling the intensity absorbed by a sensor with a PIC’s ADC. It was developed a firmware for a Low Therapy Laser Device FISSER SMART, which consisted in the firmwares for a so called “base” that controlled applicators and for the applicators. Additionally, a firmware for Zone Dosimeters was developed, which consisted in the control of High Voltage of the detector, counting pulses of the detector, adjusting the characteristic curve of the detector, calibration of the device, screen, keyboard and alarms.

• Calibration and Certification of Equipment. Calibration tasks of the equipment developed at CEADEN were performed. The zone dosimeters DZG98 and DZG10 High Voltage were serviced and calibrated as well as the detectors units were characterized and adjusted in order to get the Certificate of Calibration emitted by CPHR, Cuba. The Laser of applicators of the FISSER SMART devices was serviced and calibrated. As member of the Quality Control of Instrumentation Department of CEADEN verification tasks for the Low Laser Therapy Equipment FISSER21 production were performed.

I urval från Stockholms universitets publikationsdatabas

• Radiation studies performed on the High Luminosity ATLAS TileCal link Daughterboard

  2023. Eduardo Valdés Santurio (et al.). Journal of Instrumentation 18 (04)

  Artikel

  The new electronics of the ATLAS Tile Calorimeter for the HL-LHC interfaces the on-detector and off-detector electronics by means of a Daughterboard. The Daughterboard is positioned on-detector featuring commercial SFPs+, CERN GBTx ASICs, ProASIC FPGAs and Kintex Ultrascale FPGAs. The design minimizes single points of failure and mitigates radiation damage by means of a double redundant scheme, Triple Mode Redundancy, Xilinx Soft Error Mitigation IP, CRC/FEC for link data transfer, and SEL protection circuitry. We present an updated summary of the TID, NIEL and SEE qualification tests, and performance studies of the Daughterboard revision 6 design.

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• R&D studies for the ATLAS Tile Calorimeter Daughterboard

  2021. Eduardo Valdes Santurio. R&D studies for the ATLAS Tile Calorimeter Daughterboard

  Konferens

  The ATLAS Hadronic Calorimeter DaughterBoardinterfaces the on-detector with the off-detector electronics.The DaughterBoard features two 4.6 Gbps downlinks andtwo pairs of 9.6 Gbps uplinks powered by four SFP+Optical transceivers. The downlinks receive configurationcommands and LHC timing to be propagated to the front-end,and the uplinks transmit continuous high-speed readoutof digitized PMT samples, detector control system andmonitoring data. The design minimizes single pointsof failure and mitigates radiation damage by means ofa double-redundant scheme. To mitigate Single EventUpset rates, Xilinx Soft Error Mitigation and Triple ModeRedundancy are used. Reliability in the high speed linksis achieve by adopting Cyclic Redundancy Check in theuplinks and Forward Error Correction in the downlinks. TheDaughterBoard features a dedicated Single Event Latch-upprotection circuitry that power-cycles the board in the caseof any over-current event avoiding any possible hardwaredamages.We present a summary of the studies performed to verifythe reliability if the performance of the DaughterBoardrevision 6, and the radiation qualification tests of thecomponents used for the design.

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• A revised version of the ATLAS Tile Calorimeter link Daughterboard for the HL-LHC.

  2021. Eduardo Valdes Santurio (et al.). IEEE Transactions on Nuclear Science 68 (9), 2414-2420

  Artikel

  The ATLAS Tile Calorimeter (TileCal) readout link and control Daughter Board (DB) is the central on-detector hub of the new TileCal electronics upgrade for the high-luminosity Large Hadron Collider (HL-LHC). The DB, which has undergone gradual redesigns during development, provides the connection between the on- and off-detector electronics via bi-directional fiber optic links. Two CERN-developed, radiation hard GBTx ASICs receive LHC timing signals and configuration commands through 4.8 Gbps downlinks, which are in turn propagated to the front-end through Xilinx Kintex Ultrascale FPGAs. The Kintex FPGAs also continuously perform real-time readout and transmission of digitized Photomultiplier (PMT) samples, Detector Control System signals and monitoring data through redundant pairs of 9.6 Gbps uplinks. The DB design aims at minimizing single points of failure, and improving performance and reliability of the board. Apart from the GBTx devices, the DB design relies on radiation-qualified Commercial off-the-shelf (COTS) components. Mitigation of radiation-induced Single Event Upsets (SEU) in the FPGAs is performed by a combination of the Xilinx Soft Error Mitigation (SEM) utility and Triple Mode Redundancy (TMR) schemes in the FPGA firmware. Data integrity is protected through Forward Error Correction (FEC) in the downlinks and Cyclic Redundancy Check (CRC) error verification in the redundant uplinks. This paper presents the latest revision of the DB (version 6), a redesign that addresses Single Event Latch-up (SEL) behavior observed in the Kintex Ultrascale+ FPGAs used in the previous revision, and features a more robust power circuitry combined with an improved current monitoring scheme, enhanced performance of the ADC read-out, and improved timing performance.

  Läs mer om A revised version of the ATLAS Tile Calorimeter link Daughterboard for the HL-LHC.

• An updated design of the read out link and control board for the Phase-2 upgrade of the ATLAS Tile Calorimeter

  2019. Eduardo Valdes Santurio, Samuel Silverstein, Christian Bohm. The 39th International Conference on High Energy Physics

  Konferens

  The ATLAS hadronic Tile Calorimeter (TileCal) is being upgraded for the High Luminosity Large Hadron Collider (HL-LHC). We present a redesign of the TileCal Phase II read out link and control Daughterboard (DB). The DB has a double redundant radiation tolerant design that will provide continuous high-speed readout of digitized data samples of 12 photomultiplier channels each with two gains, while handling the timing, control and communication between the frontend and off-detector electronics, all over multi-gigabit optical links. Four SFP+ modules serve 4×9.6 Gbps uplinks and 2×4.8 Gbps downlinks, handled respectively by two re-programmable Kintex Ultrascale+ FPGAs and two CERN developed gigabit link ASICs (GBTx). Better highspeed uplink timing and improved radiation tolerance have been achieved by migrating the previous design from the Xilinx Kintex-7 FPGAs to the Kintex Ultrascale+ architecture. Preliminary TID radiation tests were performed on a Daughterboard revision 5 following the TOTAL DOSE STEADY-STATE IRRADIATION TEST METHOD ESCC22900 and the ATLAS protocol and safety factors.

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• Beam tests on the ATLAS tile calorimeter demonstrator module

  2019. Eduardo Valdes Santurio. Nuclear Instruments and Methods in Physics Research Section A 936, 115-116

  Artikel

  The Large Hadron Collider (LHC) Phase-II upgrade aims to increase the accelerator luminosity by a factor of 5-10. Due to the expected higher radiation levels and the aging of the current electronics, a new read-out system of the ATLAS experiment hadronic calorimeter (TileCal) is needed. A Demonstrator prototype of the electronics has been tested during different testbeam campaigns at the Super Proton Synchrotron (SPS) accelerator of CERN with the purpose of checking the calibration and determining the performance of the detector by exploiting the features of the interactions of different particles with matter. We present the current status and results where the Demonstrator new electronics were situated in calorimeter modules and data were collected by exposing it to beams of muons, electrons and hadrons, at various incident energies and impact angles.

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• Readiness of the ATLAS Tile Calorimeter link daughterboard for the High Luminosity LHC era

  2019. Eduardo Valdes Santurio, Samuel B. Silverstein, Christian Bohm.

  Konferens

  The Daughterboard (DB) is the read-out link and control board that interfaces the on- and offdetector electronics for the High-Luminosity Large Hadron Collider (HL-LHC) of the the ATLAS Tile Calorimeter (TileCal). The DB sends high-speed read-out of digitized Photomultiplier (PMT) samples, while receiving and distributing configuration, control and LHC timing. A redundant design based on Xilinx Soft Error Mitigation (SEM), Triple Mode Redundancy (TMR), Forward Error Correction (FEC) and CRC Cyclic Redundancy Check (CRC) strategies minimizes single failure points while withstanding single-event upsets and damage from minimum ionizing and hadronic radiation. We present the current results of the performed TID, NIEL and SEU tests, aiming to demonstrate the readiness of the Daughterboard to satisfy the radiation requirements imposed by the HL-LHC.

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• ATLAS Tile Calorimeter Link Daughterboard

  2019. Eduardo Valdes Santurio, Samuel Silverstein, Christian Bohm. Topical Workshop on Electronics for Particle Physics

  Konferens

  We have developed an updated Daughterboard design for control and readout of the upgraded ATLAS Hadronic Tile Calorimeter electronics for HL-LHC. In the new design, four SFP+ modules handle: 4×9.6 Gbps uplinks operated by two Kintex Ultrascale+ FPGAs, and 2×4.8 Gbps downlinks operated by two GBTxs. The uplink sends continuous high-speed readout of digitized PMT samples, while the downlink receives control, configuration and LHC timing. Triple Mode Redundancy (TMR), Forward Error Correction (FEC) and CRC (Cyclic Redundancy Check) strategies, plus a double redundant design with radiation tolerant components, minimize single failure points and improves resistance to single-event upsets caused by hadronic radiation. Preliminary TID and NIEL tests were performed following the ATLAS policy on radiation tolerant electronics and those specified in the European Space Components Coordination specification 22900 (ESCC22900).

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• Redesign of the ATLAS Tile Calorimeter read-out link and control board for the high-luminosity LHC era

  2019. Eduardo Valdes Santurio (et al.).

  Konferens

  The R&D for the new on-detector electronics for the Phase-II ATLAS upgrade for the High-Luminosity Large Hadron Collider (HL-LHC) has motivated progressive redesigns of the ATLAS Tile Calorimeter (TileCal) Daughterboard (DB). The DB is the read-out link and control board interface to the off-detector electronics of TileCal. The DB receives configuration commands and LHC timing via two CERN radiation-hard GBTx ASICs and two redundant 4.8 Gbps downlinks. Two Ultrascale+ FPGAs send continuous high-speed read-out of digitized Photomultiplier Tube (PMT) samples through four 9.6 Gbps uplinks. We present a DB redesign that improves the timing scheme, and enhances the radiation tolerance by mitigating Single Event Latch-up (SEL) induced errors and implementing a more robust power-up and current monitoring scheme. The design minimizes single points of failure and reduces sensitivity to Single Event Upsets (SEUs) and radiation damage by employing a double-redundant scheme, using Triple Mode Redundancy (TMR) and Xilinx Soft Error Mitigation (SEM) in the FPGAs, adopting Cyclic Redundancy Check (CRC) error verification in the uplinks and Forward Error Correction (FEC) in the downlinks.

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• Development of the read-out link and control board for the ATLAS Tile Calorimeter Upgrade

  2019. Eduardo Valdés Santurio, Samuel Bryant Silverstein, Costas Foudas.

  Avhandling (Dok)

  The Phase-II upgrade plan for the ATLAS Hadronic Tile Calorimeter facing the High-Luminosity LHC (HL-LHC) era includes approximately 1000 radiation tolerant read-out link and control boards (Daughterboards) that will provide full-granularity digital data to a fully-digital trigger system off-detector through multi-Gbps optic fibres. Different Daughterboard (DB) revisions have been developed, each successively aiming to meet the demanding HL-LHC requirements. The DB communicates with the off-detector systems via four 9.6 Gbps uplinks and two 4.8 Gbps downlinks. The DB performs high-speed read-out of digitized Photomultiplier (PMT) samples, while receiving and distributing configuration, control and LHC-synchronous timing to the front-end system. The design aims to minimize radiation-induced errors and enhance data reliability by embracing a fully double redundant design using CERN radiation hard GBTx ASICs and Xilinx FPGAs, implementing Triple Mode Redundancy (TMR), adopting Soft Error Mitigation (SEM) to correct for configuration memory Single Event Upsets (SEU), and employing Cyclic Redundancy Check (CRC) and Forward Error Correction (FEC) in the data format of the uplink and downlink, respectively. Total Ionizing Dose (TID), Non-Ionizing Energy Losses (NIEL) and Single Event Effects (SEE) radiation tests have been performed in order to assess the radiation tolerance strategies followed in the design and to qualify the DB for the HL-LHC requirements according to the ATLAS policy on radiation tolerant electronics. This thesis presents the author's contribution to the development of the DB through the different revisions, the integration of the DB to the Demonstrator and the radiation tests performed aiming to demonstrate the readiness of the DB to withstand the radiation requirements imposed by the HL-LHC. Resulting of this document, the author proposes strategies to be used in the new DB design moving forward the final design to be produced and inserted in ATLAS during the 2024-2026 period.

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• Upgrade of Tile Calorimeter of the ATLAS Detector for the High Luminosity LHC.

  2017. Eduardo Valdes Santurio. 17th International Conference on Calorimetry in Particle Physics (CALOR2016)

  Konferens

  The Tile Calorimeter (TileCal) is the hadronic calorimeter of ATLAS covering the central region of the ATLAS experiment. TileCal is a sampling calorimeter with steel as absorber and scintillators as active medium. The scintillators are read out by wavelength shifting fibers coupled to photomultiplier tubes (PMT). The analogue signals from the PMTs are amplified, shaped and digitized by sampling the signal every 25 ns. The High Luminosity Large Hadron Collider (HL-LHC) will have a peak luminosity of 5 × 1034 cm −2 s −1, five times higher than the design luminosity of the LHC. TileCal will undergo a major replacement of its on- and off-detector electronics for the high luminosity programme of the LHC in 2026. The calorimeter signals will be digitized and sent directly to the off-detector electronics, where the signals are reconstructed and shipped to the first level of trigger at a rate of 40 MHz. This will provide a better precision of the calorimeter signals used by the trigger system and will allow the development of more complex trigger algorithms. Three different options are presently being investigated for the front-end electronic upgrade. Extensive test beam studies will determine which option will be selected. Field Programmable Gate Arrays (FPGAs) are extensively used for the logic functions of the off- and on-detector electronics. One hybrid demonstrator prototype module with the new calorimeter module electronics, but still compatible with the present system, may be inserted in ATLAS at the end of 2016.

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• An Updated Front-End Data Link Design for the Phase-2 Upgrade of the ATLAS Tile Calorimeter

  2017. Samuel Silverstein, Eduardo Valdes Santurio, Christian Bohm. 2017 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC)

  Konferens

  We present a new design for the advanced Link Daughter Board (DB) for the front-end electronics upgrade of the ATLAS hadronic Tile Calorimeter. The DB provides control, configuration and continuous ADC readout for the front-end through bi-directional multi-GB/s optical links with the off-detector readout system. The DB will operate in high luminosity LHC conditions with limited detector access, so the design is fault tolerant with a high level of redundancy to avoid single-point failure modes. The new design is based on the new Xilinx Kintex Ultrascale+ FPGA family, which provides improved high-speed link timing performance and radiation tolerance, as well as better signal compatibility with the CERN-developed GBTx link and timing distribution ASICs. Two GBTx ASICs each provide redundant phase-adjusted, LHC synchronous clocks, parallel control buses and remote JTAG configuration access to the two FPGAs on the DB.

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• Technical Design Report for the Phase-II Upgrade of the ATLAS Tile Calorimeter

  2018. Yiming Abulaiti (et al.).

  Rapport

  This Technical Design Report describes the project to upgrade the ATLAS Tile Calorimeter for the operation at the High Luminosity LHC. The High Luminosity LHC is planned to begin operation in 2026 and to deliver more than ten times the integrated luminosity (up to 4000 fb"^{-1}" of the LHC Runs 1-3 combined. To achieve this integrated luminosity in a reasonable amount of time, an instantaneous luminosity of up to "7.5\times 10^{34} cm^{-2}s^{-1}" is required, corresponding to up to 200 simultaneous pp interactions per bunch crossing. The large luminosity offers the opportunity for a wealth of physics measurements but presents significant challenges to the detector as well as to the trigger and data acquisition systems in the form of increased trigger rates and detector occupancy. This document summarises the requirements and motivations for the Tile Calorimeter upgrade and gives a detailed technical description of the different components. It describes the beam tests with the prototypes in recent years and the plans for the assembly, quality assurance and the integration of the final system. The document also presents the key aspects of project management with an overview of the organisation, the schedule and the cost.

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• A radiation tolerant Data link board for the ATLAS Tile Cal upgrade

  2016. Henrik Åkerstedt (et al.). Journal of Instrumentation 11

  Artikel

  This paper describes the latest, full-functionality revision of the high-speed data link board developed for the Phase-2 upgrade of ATLAS hadronic Tile Calorimeter. The link board design is highly redundant, with digital functionality implemented in two Xilinx Kintex-7 FPGAs, and two Molex QSFP+ electro-optic modules with uplinks run at 10 Gbps. The FPGAs are remotely configured through two radiation-hard CERN GBTx deserialisers (GBTx), which also provide the LHC-synchronous system clock. The redundant design eliminates virtually all single-point error modes, and a combination of triple-mode redundancy (TMR), internal and external scrubbing will provide adequate protection against radiation-induced errors. The small portion of the FPGA design that cannot be protected by TMR will be the dominant source of radiation-induced errors, even if that area is small.

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